FIG. 1 depicts an example flow chart for integrated circuit (IC) design. As shown in FIG. 1, electronic system level (ESL) design 12 may be performed based on certain system specification/requirements 10 for a digital IC. Register-transfer-level (RTL) design 14 models the digital IC in terms of a flow of digital signals (data) between hardware registers, and logical operations performed on those digital signals. A logic synthesis process 16 turns an abstract form of desired circuit behavior at RTL into a design implementation in terms of logic gates. During a physical design process 18, circuit representations of components (e.g., devices and interconnects) of a circuit design are converted into an IC layout (e.g., geometric representations of shapes which, when manufactured in corresponding layers of materials, can ensure required functioning of the components).
The physical design process 18 usually includes several stages, such as partitioning 24 (e.g., dividing a chip into small blocks), floor planning 26 (e.g., identifying structures that should be placed close together and allocating space for the structures in such a manner as to meet goals of available space, required performance, etc.), placement 28 (e.g., assigning exact locations for various circuit components within the chip's core area), clock tree synthesis (CTS) 30 (e.g., insertion of buffers or inverters along clock paths of the design to achieve zero/minimum skew or balanced skew), routing 32 (e.g., including global routing that allocates routing resources for connections, and detailed routing that assigns routes to specific metal layers and routing tracks within the global routing resources), and timing closure 34 (e.g., modifying the design to meet timing requirements). After the physical design process 18, physical verification and sign-off 20 may be performed to determine a correct layout design for manufacturing the chip 22.
Power consumption has become important along with timing and area for integrated circuit design (e.g., for portable, battery-powered electronic devices and high performance servers). There are a number of known power management techniques, but the challenge in designing for low power consumption is usually related to the accuracy of power estimation tools. Accuracy of power estimation is generally good at later stages of circuit design (e.g., after the placement stage 28 and the routing stage 32 are completed), but then it may be too late to make architectural changes to the circuit design for reducing power consumption.
Power estimation at the RTL stage 14 can be more efficient for optimizing power consumption because at the RTL stage 14 there is enough flexibility to make high-impact changes to achieve low power consumption. However, power estimation at the RTL stage 14 may not be very accurate, as it is often difficult to evaluate the impact of the design changes on power consumption without going through the placement 28, the CTS stage 30, and the routing 32. Power estimation at the RTL stage 14 may also suffers accuracy loss because at the RTL stage 14, there is no or little knowledge of design structure and dynamic effects (e.g., glitches and poor modeling of clock and interconnect structures).
For example, design changes of clocks may be made at the RTL stage 14 for power reduction because clocks are the largest source of dynamic power consumption. Such changes at the RTL stage 14 to reduce clock power can affect physical characteristics of a clock tree structure. The clock tree structure, however, is built during the CTS stage 30 that is performed after the placement stage 28 is completed, as shown in FIG. 1. Thus, it is not easy to estimate accurately the impact of any design changes at the RTL stage 14 on clock power reduction.
Therefore, methods and systems to model and accurately estimate clock power at the RTL stage are needed.